1. Technical Field
The present disclosure relates to an integrated circuit. More particularly, the present disclosure relates to a clock and data recovery (CDR) circuit.
2. Description of Related Art
With the rapid development of manufacturing technology, the operating speed of integrated circuits has been significantly improved. In a high speed communication system, a clock and data recovery (CDR) circuit is commonly utilized for assuring that input data can be correctly read after being transferred.
As the speed of processing data increases, the noises and frequency offsets caused by a data transmitter terminal increase. To tolerate more frequency offsets, the CDR circuit requires to be operated at a higher frequency. As a result, the implementation of the CDR circuit is difficult to be achieved due to hardware limitation.
To resolve the aforementioned problem, the operating frequency of the CDR circuit can be increased by enlarging a phase step adjusted by the CDR circuit in a unit of time. However, through this arrangement, the CDR circuit cannot instantly adjust the high-speed data signal. Therefore, a heretofore-unaddressed need exists to address the aforementioned deficiencies and inadequacies.